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  • PELS
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    Pages/Slides: 73
07 May 2024

High-performance processors (e.g., GPUs, CPUs, ASICs, etc.) serve as the engine of data center computing platforms and the foundation for technical progress in areas such as artificial intelligence and autonomous vehicles. Due to the fast-growing demand for greater computational power, the electric power consumption of processors has increased dramatically in recent years and is approaching 1000 W, with core logic voltages below 1 V and peak current demand beyond 1000 A. At such high current levels, the large power distribution network (PDN) of the existing two-stage lateral power delivery (LPD) architecture can lead to a dramatic voltage drop and unacceptable conduction losses, which significantly limits processor performance, reduces system energy efficiency, and hinders data center decarbonization and densification. In pursuit of a more efficient and compact alternative to the existing solution, this talk will introduce a family of high-performance 48-V-to-1-V hybrid switched-capacitor (SC) voltage regulators, named the switching bus converter (SBC). Based on a single-stage vertical power delivery (VPD) architecture, the SBC significantly reduces the PDN size and power conversion losses. Moreover, benefiting from the hybrid SC approach, the SBC effectively leverages the greatly superior energy density of capacitors compared to magnetic components, as well as the better figure-of-merit of low-voltage switching devices over high-voltage devices. Various hardware prototypes will be presented, including a 1500-A high-efficiency converter and a high-density converter with a practical form factor for VPD.

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  • PELS
    Members: Free
    IEEE Members: $8.00
    Non-members: $12.00